Computers, Microprocessors, and Embedded Systems

Sources

1. Lecture materials
2. Giordana Francesca Brescia, embedded, “Edge AI: The Future of Artificial Intelligence in embedded systems” - 2024-09-13

History of Computers and Microprocessors

Mechanical and Electromechanical Era

Disadvantages of Mechanical and Electro-Mechanical Parts

Mechanical and electro-mechanical devices had limited computing speed and were unreliable due to their mechanical parts

Date and Key People	Highlights	Remarks/Relevance
1000 BC - Orient People	- Abacus was the first device for streamlining arithmetic operations
1642 - Blaise Pascal	- first geared calculator which enabled automatic computation	- it was much more efficient as opposed to the manual human intervention needed in the Abacus
1832 - Charles Babbage and Augusta Ada Byron	- the analytical engine was the first general-purpose computer that could store 1000 20-digit decimal numbers and programs. - In contrast to the other two, this one is not limited to specific operations. - It also worked like a modern computer, wherein “store and mill” or storage of digits through memory and executing a program to process them can be performed	- users can design their own programs

Vacuum Tube Era

Disadvantages of Vacuum Tubes

Electronic computers relied on vacuum tubes, which were not ideal because they were bulky and generated a lot of heat

Date and Key People	Highlights	Remarks/Relevance
Between 1937 and 1939 - John Vincent Atanasoff and Clifford Berry	- the Atanasoff-Berry computer was the first computer to separate data processing from memory	- this enhances the flexibility and scalability of computers: the memory’s size is now not limited to the size of the processor
1945 - John W. Mauchly and John Presper Eckert	- the ENIAC (Electronics Numerical Integrator and Calculator) was the first modern electronic computer	- it did not depend on mechanical devices, which were tethered with issues such as limited computing speed and unreliability.
1945 - John Von Nuemann	- the development of the EDVAC (Electronics Discrete Variable Computer) which incorporated the stored program computer architecture designed by Nuemann	- This addressed the issue of ENIAC which had to be reprogrammed for each task because it was not a stored program machine

Transistor Age

Disadvantages of Transistors

• Transistor being discrete resulted in manufacturing that was expensive, cumbersome, and error-prone
• making better computers required more transistors, which was difficult to carry out due to costs

Date and Key People	Highlights	Remarks
1953 - MIT (Massachusetts Institute of Technology)	- TX-0 was an experimental transistor-based computer (not sure if it was the first)	- did not rely on vacuum tubes, which suffered from being bulky and generating a lot of heat

Integrated Circuit Age

Date and Key People	Highlights	Remarks
1964 - DEC	- PDP-8 was the first minicomputer	- it was smaller and more cost-effective than mainframe computers.

Microprocessor Age

Date and Key People	Highlights	Remarks
1971 - M.E. Hoff	- 4004 was a 4-bit programmable controller and the first microprocessor - it had a clock speed of 108 KHz	- the bits referred to width of the data units and integers which a particular computer architecture used - can perform 50 KIPS (kilo instruction per second)
1972 04 - Intel	- 8008 was the first 8-bit microprocessor. - it had a clock speed of 200 KHz - it had 16 KB of addressable memory
1974 04 - Intel	- the 8080 had a clock speed of 2 MHz - it had 64 KB of addressable memory - it used NMOS logic instead of PMOS logic	- for these reasons, it ran instructions 10 times faster than the 8008 - NMOS logic is faster than PMOS logic
1976 03 - Intel	- the 8085 had an 8-bit data bus - it had 64 KB of addressable memory - it had an internal clock generator and an internal system controller - although not exact frequency was not identified in the source, it was stated to be higher than previous ones	- it can perform 769 KIPS - it had an internal clock generator as opposed to one provided by external chips - similarly it had an internal system controller instead of using extra chips. I’m guessing that this has to do with interrupt control (?) - faster due to higher clock speed
1978 06 - Intel	- 8086 was the first 16-bit microprocessor - it had a clock speed of 5-10 MHz - it had 1 MB of addressable memory - it had a 4 or 6 byte instruction cache - had a 16-bit data bus - they run in real mode (i.e., one program at a time with actual addresses in the segment registers)	- it can perform 2.5 MIPS (Mega Instructions Per Second) - the instruction cache prefetched a number of instructions before execution - was considered CISC (complex instruction set computers) because of the complexity and number of instructions it can handle - actual addresses instead of logical/virtual ones (?)
1979 06 - Intel	- the 8088 was similar with 8086 but with an 8-bit data bus instead of 16-bit
1982 02 - Intel	the 80286 had the following characteristics: - it had a 16-bit microprocessor - it had 16 MB of addressable memory - can run in real mode or protected mode	- protected mode allowed for multitasking—running more than one job currently.
1985 10 - Intel	- the 80386 was the first 32-bit microprocessor - 80386SX: 16 MB of addressable memory, 16-bit data bus and 24-bit address bus (2.5 MIPS) - 80386SL: 32 MB of addressable memory, 16-bit data bus and 25-bit address bus - 80386DX: 4 GB of addressable memory, 32-bit data bus and 32-bit address bus (6 MIPS) - compatible with earlier microprocessors - operating system can manage memory	- it can run applications that make use of GUI (Graphical User Interface), WYSIWYG (what you see is what you get), or CAD - faster clocking speed
1989 04 - Intel	- the 80486 was a 32-bit microprocessor - 32-bit data bus - 4 GB addressable memory - 80387 internal arithmetic co-processor - 8 KB internal cache memory - 80486DX: 50 MHz version (20 MIPS) - 80486DX2: double clocked version, 66 MHz instruction execution rate, with memory transfer at 33 MHz - 80486DX4: triple clocked version, 100 MHz instruction execution rate, with memory transfer at 33 MHz (54 MIPS)
1993 - Intel	- Pentium was a 64-bit microprocessor - 64-bit data bus - 4 GB memory and 16 KB cache memory - dual integer processors, allowing for the execution of two instructions per clocking period (superscalar architecture) - 5 stage pipelined structure - internal floating point coprocessor for floating-point data - the fastest version had a clock speed of 233 MHz
1995 - Intel	- Pentium Pro was a 64-bit microprocessor - 64GB memory, 16 KB L1 cache, and 256 KB L2 cache - 12-stage pipelined structure - 3 integer processor and internal floating-point coprocessor - fastest version had a clock speed of 200 MHz
1997 - Intel	- Pentium II was a 64-bit microprocessor - 64GB memory, 32 KB L1 cache, and 512 KB L2 cache - fastest version has a clock speed of 450 MHz with a 100 MHz memory bus speed - used 4 new technologies to enhance performance: Dual Independent Bus Architecture (DIB), Dynamic Execution, Intel MMX Technology, and Single-Edge Contact Cartridge (SEC)	- DIB architecture is composed of two independent buses, providing thrice the performance of single bus architecture processors - Dynamic Execution - uses multiple branch prediction, data flow analysis, and speculative execution to run instructions more efficiently - MMX (Matrix Math Extensions) for efficient multimedia and communication operations - SEC packaging enabled high frequency operation
1998 04 - Intel	- Celeron provides support for AGP graphics, ATA-33 hard disk drives, SDRAM and ACPI - The fastest version had a clock speed of 533 MHz - The original Celerons was compatible with any Intel Pentium II that supported a 66 MHz system bus - its processor card—the SEPP (Single Edge Processor Package)—lacked any form of protective sheath to protect it (unlike the Pentium II). However, it can still work with Slot 1 and use existing motherboards.	- it provided good floating-point (3d geometry calculations) and multimedia performance
1998 06 - Intel	- Pentium II Xeon was a 64-bit microprocessor - memory size: 64 GB, 32 KB L1 cache, 512 KB or 1 MB L2 cache - included big and speedy cache memories	- due to its cache memories, it could move data very quickly through the processor core
1999 Spring - Intel	- Pentium 3 was a 64-bit microprocessor - memory size: 64 GB, 32 KB L1 cache, 256 KB or 512 KB L2 cache - Fastest version can run up to 1.4 GHz	- better multimedia capabilities - Windows and Unix compatible
Early 2000 - Intel	- Pentium 4 was a 64-bit microprocessor - memory size: 64 GB, 32 KB L1 cache, 256 KB or 512 KB L2 cache - uses P6 micro architecture (like previous microprocessors) but had 20 pipeline stages (Hyper Pipeline) instead of 12 stages; thereby, improving performance greatly - support for Hyper-Threading Technology allowed programs to utilize two processors - The extreme edition had a core speed of 2.46 GHz with an integrated 2 MB L3 cache and 1066 MHz system bus - offered the following features: 1-MB L2 Advanced Transfer Cache, 16 KB L1 data cache, and Streaming SIMD Extensions 3 (SSE3).	- HT Technology led to increased performance beyond GHz and also improved efficiency by enabling the simultaneous execution of two threads of instructions - SSE2 improves the MMX technology
2001 - Intel and Hewlett-Packard	- Itanium was a 64-bit microprocessor with a 128-bit data bus - its architecture was based on EPIC (Explicitly Parallel Instruction Computing). - had the following features: 128 general purpose internal registers, 128 floating-point registers, 64 predicate registers - offered 733 and 800 MHz core speed and 2 MB and 4 MB off-die L3 cache	- Epic gave microprocessors the ability to run software instructions in parallel through software compilers (instead of complex logic circuits found in the processor) - seems to be lower in terms of clock speed (?) but maybe parallel execution counteracts that disadvantage
2003 03 - Intel	- Pentium M had a clock frequency from 1.3 GHz to 1.7 GHz. However, one version can reach up to 2.13 GHz (revised Dothan core version). - it had 1 MB L2 cache - 24.5-27 Thermal Design Power (TDP)
2005 05 26 - Intel	- Pentium D had a clock speed from 2.8 GHz to 3.2 GHz - was dual-core—can execute two cores in one physical processor - less power usage and heat generation due to adaptive processor voltage and frequency provided by the Enhanced Intel Speedstep Technology - L1 cache consisted of two 16 KB data cache and two 12 KB Micro-op execution trace cache - 2x1 L2 cache - 800 MHz front side bus - it had an execute disable bit to protect against some viruses and worms - can access bigger memory and support 64-bit OS due to Intel EM64T (Extended Memory 64 Technology) - SSE3 - for improved digital media applications
2006 07 27 0 Intel	- Core 2 was the first Duo processor cores - the Core 2 codenamed Allendale had a 2 MB L2 cache, whereas the Core 2 codenamed Conroe had a 4 MB shared L2 cache - Clocked from 2.4 GHz to 2.67 GHz - 1066 MHz front side bus - 65 watts TDP	- not sure if Duo processor core was the same with Dual processor since Pentium D had a Dual processor

The Future of Embedded Systems (Potential Future Trends)

• What is Edge Computing
  • it brings data processing closer to the source instead of relying on the cloud. This ensures reduces latency and enhances security and privacy.
    • Latency can be a significant factor in critical applications like healthcare
    • Avoiding the transfer and storage of data in the cloud helps the information avoid vulnerabilities.
• Edge Computing and Embedded Systems
  • Advanced AI algorithms can help embedded systems overcome the large computational power requirements for running sophisticated models
    • An example of a new chip that is made for edge AI is the NPU (or neural processing units), which are integrated into microcontrollers so that they can carry out complex models on embedded systems
  • Using edge AI can mitigate costs associated with cloud processing, including bandwidth, storage, and computational power costs.
    • This can also minimize the load on the cloud, which can be crucial in applications with a plenty of distributed devices—there are costs tethered to sending data.
  • It can reduce data volume and increase data transmission rate with respect to IoT devices, wherein interconnect devices obtain data and transmit it in real time.
    • For weather monitoring devices, it can allow the device to identify pertinent data to send to the cloud. In other words, the cloud does not need to receive extra data for processing. Therefore, it improves speed, responsiveness, and efficiency.
  • Challenges include the need for robust security measures and compressing and optimizing AI models so that they can function on resource-constrained devices without sacrificing too much accuracy and energy-consumption
    • despite better privacy due to local processing, they are sometimes more vulnerable compared to centralized servers